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PE43703
Product Specification
Table 7. Control Voltage
Table 10. Serial Address Word Truth Table
State
Bias Condition
Address Word
Address
Low
High
0 to +1.0 Vdc at 2 μ A (typ)
+2.6 to +5 Vdc at 10 μ A (typ)
A7
(MSB)
X
X
X
A6
X
X
X
A5
X
X
X
A4
X
X
X
A3
X
X
X
A2
L
L
L
A1
L
L
H
A0
L
H
L
Setting
000
001
010
Table 8. Latch and Clock Specifications
X
X
X
X
X
L
H
H
011
Latch Enable
0
↑
Shift Clock
↑
X
Function
Shift Register Clocked
Contents of shift register
transferred to attenuator core
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
L
L
H
H
L
H
L
H
100
101
110
111
Table 9. Parallel Truth Table
Table 11. Serial Attenuation Word Truth Table
Parallel Control Setting
Attenuation
Attenuation Word
Attenuation
D6
L
L
L
L
L
L
L
H
H
D5
L
L
L
L
L
L
H
L
H
D4
L
L
L
L
L
H
L
L
H
D3
L
L
L
L
H
L
L
L
H
D2
L
L
L
H
L
L
L
L
H
D1
L
L
H
L
L
L
L
L
H
D0
L
H
L
L
L
L
L
L
H
Setting
RF1-RF2
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.75 dB
D7
L
L
L
L
L
L
L
L
L
D6
L
L
L
L
L
L
L
H
H
D5
L
L
L
L
L
L
H
L
H
D4
L
L
L
L
L
H
L
L
H
D3
L
L
L
L
H
L
L
L
H
D2
L
L
L
H
L
L
L
L
H
D1
L
L
H
L
L
L
L
L
H
D0
(LSB)
L
H
L
L
L
L
L
L
H
Setting
RF1-RF2
Reference I.L.
0.25 dB
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.75 dB
Table 12. Serial-Addressable Register Map
Bits can either be set to logic high or logic low
MSB (last in)
D7 must be set to logic low
LSB (first in)
Q15
A7
Q14
A6
Q13
A5
Q12
A4
Q11
A3
Q10
A2
Q9
A1
Q8
A0
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
Address Word
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 18.25 dB state
at address 3:
Address word: XXXXX011
Attenuation Word: Multiply by 4 and convert to binary → 4 * 18.25 dB → 73 → 01001001
Serial Input: XXXXX01101001001
Document No. 70-0245-05 │ www.psemi.com
?2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 9 of 15
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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